It can translate (most of) the verilog constructs I use, but thats bound to be a limited test suite.
Feedback (bug reports) is welcome, and is much more useful if accompanied with a verilog code fragment, preferably with an edited version showing what you think it _should_ generate. It needs a regression suite. Most of the code I've used it on is not mine to post. If you do send me code, make it clear whether its private or not.
v2vhd -e blah.v > blah.vhd for the entity.
v2vhd blah.v > blah_rtl.vhd for the architecture.
There are various debug options only useful if you are hacking the perl.
The script indents its output somewhat. I find (particularly with earlier versions) that reading the output into an xemacs buffer in vhdl-mode and beautifying it does more good than harm.
The -s flag can be used. It attempts to find explicit parameter assigned state variables and maps them to vhdl enumerated types. This option needs more testing.